In the realization of memory circuits, a distinction is made in principle in terms of the memory architecture, the so-called NAND and NOR architectures being represented most commonly. In both architectures, semiconductor components such as one-transistor memory cells are arranged in matrix-type fashion and driven via word and bit lines.
While in NAND architectures a multiplicity of semiconductor components or memory elements are connected to one another serially and are driven via a common selection gate or a selection transistor, the respective semiconductor components in NOR architectures are organized in parallel or in matrix-type fashion, as a result of which each semiconductor component can be selected individually.
FIG. 1A shows a simplified illustration of a so-called SNOR architecture (Selective NOR), in which, in contrast to the NOR architecture with a “common source” construction, the individual memory elements SE1, SE2, . . . are selectively driven via a respective source line SL1, SL2, . . . and via a respective drain line DL1, DL2, . . . . This selective driving is carried out by respective bit line controllers BLC, which realize the common bit lines BL1, BL2. In this way, it is possible to carry out further shrinkage or more extensive integration of semiconductor circuit arrangements, since the SNOR architecture together with the “uniform channel programming” (UCP) does not rely on a predetermined minimum cell transistor length or channel length.
FIG. 1B shows a simplified illustration of a conventional layout of the SNOR architecture in accordance with FIG. 1A. In accordance with FIG. 1B, the switching elements or memory elements SE1, SE2, . . . are formed in active areas AA of a semiconductor substrate which have a substantially straight strip-type structure. The multiplicity of strip-type active areas AA arranged in columns have superposed on them, in rows, layer stacks or word line stacks WL1, WL2, . . . that are likewise formed in strip-type fashion. Each crossover point or overlap area between such a strip-type active area AA and a word line stack WL formed in strip-type fashion thus constitutes a multiplicity of switching elements or memory elements SE.
Contacts are used for making contact with respective drain regions D and source regions S. The contacts are usually formed in the active areas AA, but they may often also reach into an adjoining isolation region STI (Shallow Trench Isolation). In a further overlying layer, which represents a first metallization layer, there are then situated the source lines SL1, SL2, . . . and also the drain lines DL1, DL2, . . . for the respective bit lines BL. In this case, the drain lines are connected to the associated drain regions D of the active area AA via corresponding contacts KD, the source lines SL being connected to the associated source regions S via corresponding contacts KS in the same way.
Such a conventional bit line structure, on account of the additional source lines, uses metallization that is more than twice as dense compared with a “common source” architecture, which represents a limiting factor for more extensive integration.
In order to improve the integration density, it has been proposed in accordance with German Patent DE 100 62 245 A1 to form the source and drain lines sublithographically as spacers at an insulating fin and to enable contact to be made with the associated source and drain regions by an additional insulating layer with corresponding openings. However, the space requirement, on account of the source and drain lines that are formed at the substrate surface and lie parallel, is still relatively high and prevents more extensive integration.
FIGS. 2A and 2B show a simplified equivalent circuit diagram and also a simplified sectional view of a further conventional bit line structure, as is known for example from U.S. Pat. No. 6,438,030 B1.
In accordance with FIGS. 2A and 2B, the drain line DL1, DL2, . . . is again formed as a surface bit line at a surface of a substrate 100, in which are formed mutually insulated p-type wells 101, 102, . . . for the realization of a buried source line SL1, SL3, . . . in the semiconductor substrate.
For contact-connecting the respective source regions S or 1114, 1112 to the source line SL or the p-type wells 101, 102, . . . , a buried strap BS is formed as a p-type doping region 1113 in the source regions S or 1114 and 1112. The buried strap is connected to the p-type well 101 or the source line. Via a silicide layer 1116, each source region of the switching elements or memory elements SE is electrically connected to the buried strap BS or 1113 and thus to the p-type well 101 or the buried source line. On the other hand, the drain regions D or the doping regions 1111 and 1115 in accordance with FIG. 2B are electrically connected to the surface bit line DL1 via contacts 1118. Furthermore, each p-type well or buried source line 101 is electrically connected via a p-type diffusion region 1010 and an associated contact to a source line SL1 routed at the surface.
The integration density can be considerably improved in this way, since at least a large part of the source line is formed as a p-type well region in a manner “buried” in the semiconductor substrate and correspondingly relaxes the requirements made of the metallization above the substrate surface.
However, the silicide connection layers 1116, on account of the spacers (not-illustrated) at the word line stacks of the memory elements SE, have only a small overlap and consequently cause a high contact resistance with respect to the p-type well 101 or with respect to the source line. In the same way, the conductivity of the p-type well 101 or of the buried source line also represents a limiting factor since either a conductivity is correspondingly low given a low doping of the p-type well 101 or the breakdown voltages of the semiconductor component are correspondingly impaired given a high doping of the p-type well 101.
Furthermore, U.S. Pat. No. 6,008,522 discloses a buried bit line formed in a trench, respective source and drain regions being formed at its upper edges in a self-aligning manner by outdiffusion.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.